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ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 16-bit analog-to-digital converters for temperature sensors check for samples: ads1146 , ads1147 , ads1148 1 features description the ads1146, ads1147, and ads1148 are highly- 23 ? 16 bits, no missing codes integrated, precision, 16-bit analog-to-digital ? data output rates up to 2ksps converters (adcs). the ads1146/7/8 feature an ? single-cycle settling for all data rates onboard, low-noise, programmable gain amplifier (pga), a precision delta-sigma adc with a single- ? simultaneous 50/60hz rejection at 20sps cycle settling digital filter, and an internal oscillator. ? 4 differential/7 single-ended inputs (ads1148) the ads1147 and ads1148 also provide a built-in ? 2 differential/3 single-ended inputs (ads1147) voltage reference with 10ma output capacity, and two matched programmable current digital-to-analog ? matched current source dacs converters (dacs). the ads1146/7/8 provide a ? internal voltage reference complete front-end solution for temperature sensor ? sensor burnout detection applications including thermal couples, thermistors, and resistance temperature detectors (rtds). ? 4/8 general-purpose i/os (ads1147/8) ? internal temperature sensor an input multiplexer supports four differential inputs for the ads1148, two for the ads1147, and one for ? power supply and v ref monitoring the ads1146. in addition, the multiplexer has a (ads1147/8) sensor burnout detect, voltage bias for ? self and system calibration thermocouples, system monitoring, and general- ? spi ? -compatible serial interface purpose digital i/os (ads1147 and ads1148). the onboard, low-noise pga provides selectable gains of ? analog supply operation: 1 to 128. the delta-sigma modulator and adjustable +2.7v to +5.25v unipolar, 2.5v bipolar digital filter settle in only one cycle, for fast channel ? digital supply: +2.7v to +5.25v cycling when using the input multiplexer, and support ? operating temperature ? 40 c to +125 c data rates up to 2ksps. for data rates of 20sps or less, both 50hz and 60hz interference are rejected by the filter. applications ? temperature measurement the ads1146 is offered in a small tssop-16 package, the ads1147 is available in a tssop-20 ? rtds, thermocouples, and thermistors package, and the ads1148 is available in tssop-28 ? pressure measurement and qfn-32 packages. all three devices operate over ? industrial process control the extended specified temperature range of ? 40 c to +105 c. 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 spi is a trademark of motorola, inc. 3 all other trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2009 ? 2012, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. input mux 3rd order ds modulator refp refn pga burnout detect burnout detect dvdd dgnd ads1146 avss ain0ain1 sclkdin drdy dout/drdy cs start reset avdd internal oscillator adjustable digital filter serial interface and control clk input mux 3rd order ds modulator refp1 refn1 vrefout vrefcom refp0/ gpio0 refn0/ gpio1 burnout detect burnout detect dvdd dgnd iexc1 avss ain0/iexc ain1/iexc ain2/iexc/gpio2 ain3/iexc/gpio3 ain4/iexc/gpio4 ain5/iexc/gpio5 ain6/iexc/gpio6 ain7/iexc/gpio7 ads1148 only sclkdin drdy dout/drdy cs start reset avdd iexc2 internal oscillator voltage reference serial interface and control v bias gpio clk ads1148 only ads1147ads1148 pga system monitor adjustable digital filter dualcurrent dacs vref mux ads1148 only v bias
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. package/ordering information (1) dual sensor excitation number of voltage current package- product resolution inputs reference sources lead 1 differential ads1246 24 bits or external no tssop-16 1 single-ended 2 differential ads1247 24 bits or internal or external yes tssop-20 3 single-ended 4 differential ads1248 24 bits or internal or external yes tssop-28 7 single-ended 1 differential ads1146 16 bits or external no tssop-16 1 single-ended 2 differential ads1147 16 bits or internal or external yes tssop-20 3 single-ended 4 differential 16 bits or internal or external yes tssop-28 7 single-ended ads1148 4 differential 16 bits or internal or external yes qfn-32 7 single-ended (1) for the most current package and ordering information, see the package option addendum at the end of this document, or visit the device product folder on www.ti.com . absolute maximum ratings (1) over operating free-air temperature range, unless otherwise noted. ads1146, ads1147, ads1148 unit avdd to avss ? 0.3 to +5.5 v avss to dgnd ? 2.8 to +0.3 v dvdd to dgnd ? 0.3 to +5.5 v 100, momentary ma input current 10, continuous ma analog input voltage to avss avss ? 0.3 to avdd + 0.3 v digital input voltage to dgnd ? 0.3 to dvdd + 0.3 v maximum junction temperature +150 c operating temperature range ? 40 to +125 c storage temperature range ? 60 to +150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. exposure to absolute- maximum-rated conditions for extended periods may affect device reliability. 2 copyright ? 2009 ? 2012, texas instruments incorporated
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 electrical characteristics minimum/maximum specifications apply from ? 40 c to +105 c. typical specifications are at +25 c. all specifications at avdd = +5v, dvdd = +3.3v, avss = dgnd = 0v, v ref = +2.048v, and oscillator frequency = 4.096mhz, unless otherwise noted. ads1146, ads1147, ads1148 parameter conditions min typ max unit analog inputs full-scale input voltage v ref /pga (1) v (v in = adcinp ? adcinn) common-mode input range v differential input current 100 pa 1, 2, 4, 8, 16, 32, pga gain settings 64, 128 burnout current source 0.5, 2, or 10 a bias voltage (avdd + avss)/2 v bias voltage output impedance 400 ? system performance resolution no missing codes 16 bits 5, 10, 20, 40, 80, data rate 160, 320, 640, sps 1000, 2000 integral nonlinearity (inl) differential input, end point fit, pga = 1 0.5 1 lsb offset error after calibration 1 lsb pga = 1 100 nv/ c offset drift pga = 128 15 nv/ c gain error excluding v ref errors 0.5 % pga = 1, excludes v ref drift 1 ppm/ c gain drift pga = 128, excludes v ref drift ? 3.5 ppm/ c adc conversion time single-cycle settling see table 12 noise see table 1 and table 2 normal-mode rejection see table 5 at dc, pga = 1 90 db common-mode rejection at dc, pga = 32 100 db power-supply rejection avdd, dvdd at dc 100 db voltage reference input voltage reference input (avdd ? 0.5 v (v ref = v refp ? v refn ) avss) ? 1 negative reference input (refn) avss ? 0.1 refp ? 0.5 v positive reference input (refp) refn + 0.5 avdd + 0.1 v reference input current 30 na on-chip voltage reference output voltage 2.038 2.048 2.058 v output current (2) 10 ma load regulation 50 v/ma drift (3) t a = ? 40 c to +105 c 20 50 ppm/ c startup time see table 6 s (1) for v ref > 2.7v, the analog input differential voltage should not exceed 2.7v/pga (2) do not exceed this loading on the internal voltage reference. (3) specified by the combination of design and final production test. copyright ? 2009 ? 2012, texas instruments incorporated 3 (v )(gain) in 2 avss 0.1v + + avdd 0.1v - - (v )(gain) in 2
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com electrical characteristics (continued) minimum/maximum specifications apply from ? 40 c to +105 c. typical specifications are at +25 c. all specifications at avdd = +5v, dvdd = +3.3v, avss = dgnd = 0v, v ref = +2.048v, and oscillator frequency = 4.096mhz, unless otherwise noted. ads1146, ads1147, ads1148 parameter conditions min typ max unit current sources (idacs) 50, 100, 250, output current 500, 750, 1000, a 1500 voltage compliance all currents avdd ? 0.7 v initial error all currents, each idac ? 6 1.0 6 % of fs initial mismatch all currents, between idacs 0.03 % of fs temperature drift each idac 200 ppm/ c temperature drift matching between idacs 10 ppm/ c system monitors voltage t a = +25 c 118 mv temperature sensor reading drift 405 v/ c general-purpose input/output (gpio) v ih 0.7avdd avdd v v il avss 0.3avdd v logic levels v oh i oh = 1ma 0.8avdd v v ol i ol = 1ma avss 0.2 avdd v digital input/output (other than gpio) v ih 0.7dvdd dvdd v v il dgnd 0.3dvdd v logic levels v oh i oh = 1ma 0.8dvdd v v ol i ol = 1ma dgnd 0.2 dvdd v input leakage dgnd < v digital in < dvdd 10 a frequency 1 4.5 mhz clock input (clk) duty cycle 25 75 % internal oscillator frequency 3.89 4.096 4.3 mhz power supply dvdd 2.7 5.25 v avss ? 2.5 0 v avdd avss + 2.7 avss + 5.25 v normal mode, dvdd = 5v, 230 a data rate = 20sps, internal oscillator dvdd current normal mode, dvdd = 3.3v, 210 a data rate = 20sps, internal oscillator sleep mode 0.2 a converting, avdd = 5v, 225 a data rate = 20sps, external reference converting, avdd = 3.3v, 212 a data rate = 20sps, external reference avdd current sleep mode 0.1 a additional current with internal reference 180 a enabled avdd = dvdd = 5v, data rate = 20sps, 2.3 mw external reference, internal oscillator power dissipation avdd = dvdd = 3.3v, data rate = 20sps, 1.4 mw external reference, internal oscillator temperature range specified ? 40 +105 c operating ? 40 +125 c storage ? 60 +150 c 4 copyright ? 2009 ? 2012, texas instruments incorporated
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 thermal information ads1146, ads1147, ads1148 thermal metric (1) units pw 28 ja junction-to-ambient thermal resistance (2) 79.5 jc(top) junction-to-case(top) thermal resistance (3) 31.8 jb junction-to-board thermal resistance (4) 40.9 c/w jt junction-to-top characterization parameter (5) 3.0 jb junction-to-board characterization parameter (6) 41.1 jc(bottom) junction-to-case(bottom) thermal resistance (7) n/a (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . (2) the junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a jedec-standard, high-k board, as specified in jesd51-7, in an environment described in jesd51-2a. (3) the junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. no specific jedec- standard test exists, but a close description can be found in the ansi semi standard g30-88. (4) the junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the pcb temperature, as described in jesd51-8. (5) the junction-to-top characterization parameter, jt , estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining ja , using a procedure described in jesd51-2a (sections 6 and 7). (6) the junction-to-board characterization parameter, jb , estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining ja , using a procedure described in jesd51-2a (sections 6 and 7). (7) the junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. no specific jedec standard test exists, but a close description can be found in the ansi semi standard g30-88. copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 5 product folder link(s): ads1146 ads1147 ads1148
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com pin configurations rhb package qfn-32 (top view) 6 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148 din sclk ncnc nc nc dvdd dgnd ain3/iexc/gpio3 ain2/iexc/gpio2 ain7/iexc/gpio7 ain6/iexc/gpio6 ain5/iexc/gpio5 ain4/iexc/gpio4 ain1/iexc ain0/iexc 1 2 3 4 5 6 7 8 24 2322 21 20 19 18 17 dout/drdy 32 clk 9 drdy 31 reset 10 cs 30 refp0/gpio0 11 start 29 refn0/gpio1 12 avdd 28 refp1 13 avss 27 refn1 14 iexc1 26 vrefout 15 iexc2 25 vrefcom 16
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 ads1148 (qfn-32) pin descriptions name pin no. function description din 1 digital input serial data input sclk 2 digital input serial clock input nc 3 not connected pin can be grounded or left disconnected nc 4 not connected pin can be grounded or left disconnected nc 5 not connected pin can be grounded or left disconnected nc 6 not connected pin can be grounded or left disconnected dvdd 7 digital digital power supply dgnd 8 digital digital ground clk 9 digital input external clock input. tie this pin to dgnd to activate the internal oscillator. reset 10 digital input chip reset (active low). returns all register values to reset values. analog input; refp0/gpio0 11 positive external reference input 0, or general-purpose digital input/output pin 1 digital in/out analog input; refn0/gpio1 12 negative external reference input 0, or general-purpose digital input/output pin 1 digital in/out refp1 13 analog input positive external reference 1 input refn1 14 analog input negative external reference 1 input vrefout 15 analog output positive internal reference voltage output negative internal reference voltage output. connect this pin to avss when using a unipolar vrefcom 16 analog output supply, or to the midvoltage of the power supply when using a bipolar supply. ain0/iexc 17 analog input analog input 0, optional excitation current output ain1/iexc 18 analog input analog input 1, optional excitation current output analog input; ain4/iexc/gpio4 19 analog input 4, optional excitation current output, or general-purpose digital input/output pin 4 digital in/out analog input; ain5/iexc/gpio5 20 analog input 5, optional excitation current output, or general-purpose digital input/output pin 5 digital in/out analog input; ain6/iexc/gpio6 21 analog input 6, optional excitation current output, or general-purpose digital input/output pin 6 digital in/out analog input; ain7/iexc/gpio7 22 analog input 7, optional excitation current output, or general-purpose digital input/output pin 7 digital in/out analog input; ain2/iexc/gpio2 23 analog input 2, optional excitation current output, or general-purpose digital input/output pin 2 digital in/out analog input; ain3/iexc/gpio3 24 analog input 3, optional excitation current output, or general-purpose digital input/output pin 3 digital in/out iexc2 25 analog output excitation current output 2 iexc1 26 analog output excitation current output 1 avss 27 analog negative analog power supply avdd 28 analog positive analog power supply start 29 digital input conversion start. see text for complete description. digital input chip cs 30 chip select (active low) select (active low) drdy 31 digital output data ready (active low) serial data output, or data out combined with data ready (active low when drdy function dout/ drdy 32 digital output enabled) copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 7 product folder link(s): ads1146 ads1147 ads1148
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com pw package tssop-16 (top view) ads1146 (tssop-16) pin descriptions name pin no. function description dvdd 1 digital digital power supply dgnd 2 digital digital ground clk 3 digital input external clock input. tie this pin to dgnd to activate the internal oscillator. reset 4 digital input chip reset (active low). returns all register values to reset values. refp 5 analog input positive external reference input refn 6 analog input negative external reference input ainp 7 analog input positive analog input ainn 8 analog input negative analog input avss 9 analog negative analog power supply avdd 10 analog positive analog power supply start 11 digital input conversion start. see text for description of use. cs 12 digital input chip select (active low) drdy 13 digital output data ready (active low) serial data out output, or dout/ drdy 14 digital output data out combined with data ready (active low when drdy function enabled) din 15 digital input serial data input sclk 16 digital input serial clock input 8 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148 dvdd dgnd clk reset refp refn ainp ainn sclkdin dout/drdy drdy cs start avdd avss 12 3 4 5 6 7 8 1615 14 13 1211 10 9 ads1146
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 pw package tssop-20 (top view) ads1147 (tssop-20) pin descriptions name pin no. function description dvdd 1 digital digital power supply dgnd 2 digital digital ground clk 3 digital input external clock input. tie this pin to dgnd to activate the internal oscillator. reset 4 digital input chip reset (active low). returns all register values to reset values. analog input positive external reference input, or refp0/gpio0 5 digital in/out general-purpose digital input/output pin 0 analog input negative external reference input, or refn0/gpio1 6 digital in/out general-purpose digital input/output pin 1 vrefout 7 analog output positive internal reference voltage output negative internal reference voltage output. connect this pin to avss when using a unipolar vrefcom 8 analog output supply, or to the midvoltage of the power supply when using a bipolar supply. ain0/iexc 9 analog input analog input 0, optional excitation current output ain1/iexc 10 analog input analog input 1, optional excitation current output analog input analog input 2, optional excitation current output, or ain2/iexc/gpio2 11 digital in/out general-purpose digital input/output pin 2 analog input analog input 3, with or without excitation current output, or ain3/iexc/gpio3 12 digital in/out general-purpose digital input/output pin 3 avss 13 analog negative analog power supply avdd 14 analog positive analog power supply start 15 digital input conversion start. see text for description of use. cs 16 digital input chip select (active low) drdy 17 digital output data ready (active low) serial data out output, or dout/ drdy 18 digital output data out combined with data ready (active low when drdy function enabled) din 19 digital input serial data input sclk 20 digital input serial clock input copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 9 product folder link(s): ads1146 ads1147 ads1148 dvdd dgnd clk reset refp0/gpio0 refn0/gpio1 vrefout vrefcom ain0/iexc ain1/iexc sclkdin dout/drdy drdy cs start avdd avss ain3/iexc/gpio3 ain2/iexc/gpio2 12 3 4 5 6 7 8 9 10 2019 18 17 16 15 14 1312 11 ads1147
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com pw package tssop-28 (top view) 10 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148 dvdd dgnd clk reset refp0/gpio0 refn0/gpio1 refp1 refn1 vrefout vrefcom ain0/iexc ain1/iexc ain4/iexc/gpio4 ain5/iexc/gpio5 sclkdin dout/drdy drdy cs start avdd avss iexc1 iexc2 ain3/iexc/gpio3 ain2/iexc/gpio2 ain7/iexc/gpio7 ain6/iexc/gpio6 12 3 4 5 6 7 8 9 1011 12 13 14 2827 26 25 24 23 22 21 20 19 18 17 16 15 ads1148
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 ads1148 (tssop-28) pin descriptions name pin no. function description dvdd 1 digital digital power supply dgnd 2 digital digital ground clk 3 digital input external clock input. tie this pin to dgnd to activate the internal oscillator. reset 4 digital input chip reset (active low). returns all register values to reset values. refp0/gpio0 5 analog input positive external reference input 0, or general-purpose digital input/output pin 0 refn0/gpio1 6 analog input negative external reference 0 input, or general-purpose digital input/output pin 1 refp1 7 analog input positive external reference 1 input refn1 8 analog input negative external reference 1 input vrefout 9 analog output positive internal reference voltage output negative internal reference voltage output. connect this pin to avss when using a unipolar vrefcom 10 analog output supply, or to the midvoltage of the power supply when using a bipolar supply. ain0/iexc 11 analog input analog input 0, optional excitation current output ain1/iexc 12 analog input analog input 1, optional excitation current output analog input ain4/iexc/gpio4 13 analog input 4, optional excitation current output, or general-purpose digital input/output pin 4 digital in/out analog input ain5/iexc/gpio5 14 analog input 5, optional excitation current output, or general-purpose digital input/output pin 5 digital in/out analog input ain6/iexc/gpio6 15 analog input 6, optional excitation current output, or general-purpose digital input/output pin 6 digital in/out analog input ain7/iexc/gpio7 16 analog input 7, optional excitation current output, or general-purpose digital input/output pin 7 digital in/out analog input ain2/iexc/gpio2 17 analog input 2, optional excitation current output, or general-purpose digital input/output pin 2 digital in/out analog input ain3/iexc/gpio3 18 analog input 3, optional excitation current output, or general-purpose digital input/output pin 3 digital in/out iexc2 19 analog output excitation current output 2 iexc1 20 analog output excitation current output 1 avss 21 analog negative analog power supply avdd 22 analog positive analog power supply start 23 digital input conversion start. see text for complete description. cs 24 digital input chip select (active low) drdy 25 digital output data ready (active low) serial data out output, or data out combined with data ready (active low when drdy function dout/ drdy 26 digital output enabled) din 27 digital input serial data input sclk 28 digital input serial clock input copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 11 product folder link(s): ads1146 ads1147 ads1148
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com timing diagrams figure 1. serial interface timing timing characteristics for figure 1 (1) symbol description min max unit t cssc cs low to first sclk high (set up time) 10 ns t sccs sclk low to cs high (hold time) 7 t osc (2) t dist din set up time 5 ns t dihd din hold time 5 ns t dopd sclk rising edge to new data valid 50 (3) ns t dohd dout hold time 0 ns 500 ns t sclk sclk period 64 conversions t spwh sclk pulse width high 0.25 0.75 t sclk t spwl sclk pulse width low 0.25 0.75 t sclk t csdo cs high to dout high impedance 10 ns t cspw chip select high pulse width 5 t osc (1) drdy mode bit = 0. (2) t osc = 1/f clk . the default clock frequency f clk = 4.096mhz. (3) for dvdd > 3.6v, t dopd = 180ns. figure 2. spi interface timing to allow conversion result loading (4) (5) timing characteristics for figure 2 symbol description min max unit t pwh drdy pulse width high 3 t osc t s td sclk low prior to drdy low 5 t osc t dts drdy falling edge to sclk rising edge 1/f clk ns (4) this timing diagram is applicable only when the cs pin is low. sclk need not be low during t std when cs is high. (5) sclk should only be sent in multiples of eight during partial retrieval of output data. 12 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148 sclk (3) 1 2 3 8 7 6 5 4 drdy t std t dts t pwh sclk dout[7] dout[6] dout[5] dout[4] dout[1] dout[0] din[0] din[7] din[6] din[5] din[4] din[1] din[0] cs dout/ (1) drdy din t cssc t dist t dihd t sclk t sccs t csdo t dopd t spwl t spwh t dohd t cspw
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 figure 3. minimum start pulse width timing characteristics for figure 3 symbol description min max unit t start start pulse width high 3 t osc figure 4. reset pulse width and spi communication after reset timing characteristics for figure 4 symbol description min max unit t reset reset pulse width low 4 t osc t rhsc reset high to spi communication start 0.6 (1) ms (1) for f osc = 4.096mhz, scales proportionately with f osc frequency. copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 13 product folder link(s): ads1146 ads1147 ads1148 t start start sclk cs reset t reset t rhsc
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com noise performance the ads1146/7/8 noise performance can be optimized by adjusting the data rate and pga setting. as the averaging is increased by reducing the data rate, the noise drops correspondingly. increasing the pga value reduces the input-referred noise, particularly useful when measuring low-level signals. table 1 and table 2 summarize noise performance of the ads1146/7/8. the data are representative of typical noise performance at t = +25 c. the data shown are the result of averaging the readings from multiple devices and were measured with the inputs shorted together. table 1 lists the input-referred noise in units v pp . in many of the settings, especially at lower data rates, the inherent device noise is less than 1lsb. for these cases, the noise is rounded up to 1lsb. table 2 lists the corresponding data in units of enob (effective number of bits) where: enob = ln(full-scale range/noise)/ln(2) (1) table 1. noise in v pp at v ref = 2.048v, avdd = 5v, and avss = 0v pga setting data rate (sps) 1 2 4 8 16 32 64 128 5 62.50 (1) 31.25 (1) 15.63 (1) 7.81 (1) 3.91 (1) 1.95 (1) 0.98 (1) 0.49 (1) 10 62.50 (1) 31.25 (1) 15.63 (1) 7.81 (1) 3.91 (1) 1.95 (1) 0.98 (1) 0.49 (1) 20 62.50 (1) 31.25 (1) 15.63 (1) 7.81 (1) 3.91 (1) 1.95 (1) 0.98 (1) 0.55 40 62.50 (1) 31.25 (1) 15.63 (1) 7.81 (1) 3.91 (1) 1.95 (1) 0.98 (1) 0.75 80 62.50 (1) 31.25 (1) 15.63 (1) 7.81 (1) 3.91 (1) 1.95 (1) 1.09 0.98 160 62.50 (1) 31.25 (1) 15.63 (1) 7.81 (1) 3.91 (1) 1.95 (1) 1.88 1.57 320 62.50 (1) 35.30 17.52 8.86 4.35 3.03 2.44 2.34 640 93.06 45.20 18.73 12.97 6.51 4.20 3.69 3.50 1000 284.59 129.77 61.30 33.04 16.82 9.08 5.42 4.65 2000 273.39 130.68 67.13 36.16 19.22 9.87 6.93 6.48 (1) peak-to-peak noise rounded up to 1lsb. table 2. effective number of bits from peak-to-peak noise at v ref = 2.048v, avdd = 5v, and avss = 0v pga setting data rate (sps) 1 2 4 8 16 32 64 128 5 16 16 16 16 16 16 16 16 10 16 16 16 16 16 16 16 16 20 16 16 16 16 16 16 16 15.8 40 16 16 16 16 16 16 16 15.4 80 16 16 16 16 16 16 15.8 15.0 160 16 16 16 16 16 16 15.1 14.3 320 16 15.8 15.8 15.8 15.8 15.4 14.7 13.7 640 15.4 15.5 15.7 15.3 15.3 14.9 14.1 13.2 1000 13.8 13.9 14.0 13.9 13.9 13.8 13.5 12.7 2000 13.9 13.9 13.9 13.8 13.7 13.7 13.2 12.3 14 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 typical characteristics at t a = +25 c, avdd = 5v, v ref = 2.5v, and avss = 0v, unless otherwise noted. analog current digital current vs temperature vs temperature figure 5. figure 6. analog current vs temperature digital current vs temperature figure 7. figure 8. analog current vs data rate digital current vs data rate figure 9. figure 10. copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 15 product folder link(s): ads1146 ads1147 ads1148 330310 290 270 250 230 210 190 temperature ( c) digital current ( a) m - 40 - 20 0 20 40 60 80 100 120 5/10/20sps 40/80/160sps 320/640/1ksps 2ksps dvdd = 5v 800700 600 500 400 300 200 100 0 temperature ( c) analog current ( a) m - 40 - 20 0 20 40 60 80 100 120 5/10/20sps 40/80/160sps 320/640/1ksps 2ksps avdd = 5v 700600 500 400 300 200 100 0 temperature ( c) analog current ( a) m - 40 - 20 0 20 40 60 80 100 120 5/10/20sps 40/80/160sps 320/640/1ksps 2ksps avdd = 3.3v 310290 270 250 230 210 190 temperature ( c) digital current ( a) m - 40 - 20 0 20 40 60 80 100 120 5/10/20sps 40/80/160sps 320/640/1ksps 2ksps dvdd = 3.3v 600550 500 450 400 350 300 250 200 150 100 data rate (sps) analog current ( a) m 5 10 20 40 80 160 320 640 1000 2000 avdd = 5v avdd = 3.3v 290270 250 230 210 190 170 data rate (sps) digital current ( a) m 5 10 20 40 80 160 320 640 1000 2000 dvdd = 3.3v dvdd = 5v
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com typical characteristics (continued) at t a = +25 c, avdd = 5v, v ref = 2.5v, and avss = 0v, unless otherwise noted. data rate error vs temperature idac line regulation figure 11. figure 12. idac drift internal reference long term drift figure 13. figure 14. idac voltage compliance idac voltage compliance figure 15. figure 16. 16 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148 ?120 ?100 ?80 ?60 ?40 ?20 0 0 200 400 600 800 1000 time (hours) reference drift (ppm) 32 units g000 0.0040.003 0.002 0.001 0 - 0.001 - 0.002 - 0.003 - 0.004 temperature ( c) iexc1 iexc2 ( - m a) - 40 - 20 0 20 40 60 80 100 120 1.5ma setting, 10 units 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 0 1 2 3 4 5 voltage (v) normalized idac current 50a100a 250a 500a 750a 1ma 1.5ma 0.98 0.985 0.99 0.995 1 1.005 1.01 0 1 2 3 4 5 voltage (v) normalized idac current 1.0021.001 1.000 0.999 0.998 0.997 0.996 0.995 0.994 0.993 0.992 0.991 avdd (v) normalized output current 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 750 a m 250 a m 1.5ma 500 a m 100 a m 1ma 50 a m idac current settings 3.02.5 2.0 1.5 1.0 0.5 0 0.51.0 1.5 2.0 2.5 3.0 -- - - - - temperature ( c) data rate error (%) - 40 - 20 0 20 40 60 80 100 120 dvdd = 5v dvdd = 3.3v
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 general description overview the ads1147 and ads1148 also include a flexible the ads1146, ads1147 and ads1148 are highly input multiplexer with system monitoring capability integrated 24-bit data converters. each device and general-purpose i/o settings, a very low-drift includes a low-noise, high-impedance programmable voltage reference, and two matched current sources gain amplifier (pga), a delta-sigma ( ) adc with an for sensor excitation. figure 17 and figure 18 show adjustable single-cycle settling digital filter, internal the various functions incorporated into each device. oscillator, and a simple but flexible spi-compatible serial interface. figure 17. ads1146 diagram figure 18. ads1147, ads1148 diagram copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 17 product folder link(s): ads1146 ads1147 ads1148 input mux 3rd order ds modulator refp refn pga burnout detect burnout detect dvdd dgnd ads1146 avss ain0ain1 sclkdin drdy dout/drdy cs start reset avdd internal oscillator adjustable digital filter serial interface and control clk v bias input mux 3rd order ds modulator refp1 refn1 vrefout vrefcom refp0/ gpio0 refn0/ gpio1 burnout detect burnout detect dvdd dgnd iexc1 avss ain0/iexc ain1/iexc ain2/iexc/gpio2 ain3/iexc/gpio3 ain4/iexc/gpio4 ain5/iexc/gpio5 ain6/iexc/gpio6 ain7/iexc/gpio7 ads1148 only sclkdin drdy dout/drdy cs start reset avdd iexc2 internal oscillator voltage reference serial interface and control v bias gpio clk ads1148 only ads1147ads1148 pga system monitor adjustable digital filter dualcurrent dacs vref mux ads1148 only
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com adc input and multiplexer any analog input pin can be selected as the positive input or negative input through the mux0 register. the ads1146/7/8 adc measures the input signal the ads1146/7/8 have a true fully differential mode, through the onboard pga. all analog inputs are meaning that the input signal range can be from connected to the internal ain p or ain n analog inputs ? 2.5v to +2.5v (when avdd = 2.5v and through the analog multiplexer. a block diagram of avss = ? 2.5v). the analog input multiplexer is shown in figure 19 . through the input multiplexer, the ambient the input multiplexer connects to eight (ads1148), temperature (internal temperature sensor), avdd, four (ads1147), or two (ads1146) analog inputs that dvdd, and external reference can all be selected for can be configured as single-ended inputs, differential measurement. refer to the system monitor section inputs, or in a combination of single-ended and for details. differential inputs. the multiplexer also allows the on- chip excitation current and/or bias voltage to be on the ads1147 and ads1148, the analog inputs selected to a specific channel. can also be configured as general-purpose inputs/outputs (gpios). see the general-purpose digital i/o section for more details. figure 19. analog input multiplexer circuit 18 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148 system monitors temperature diode vrefpvrefn vrefp1/4vrefn1/4 vrefp0/4vrefn0/4 avdd/4 avss/4 dvdd/4 dgnd/4 ads1148 only ads1147/8 only vbias ain0ain1 vbias ain2 vbias ain3 vbias ain4 vbias ain5 vbias ain6 vbias ain7 avdd idac1 idac2 avdd vbias pga ain p avss avdd burnout current source (0.5 a, 2 a, 10 m m m a) burnout current source (0.5 a, 2 a, 10 m m m a) ain n to adc avss avss avss avss avss avss avss avss avdd avdd avdd avdd avdd avdd avdd avdd avdd avdd
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 esd diodes protect the adc inputs. to prevent these v ref = v refp ? v refn diodes from turning on, make sure the voltages on in the case of the ads1146, these pins are dedicated the input pins do not go below avss by more than inputs. for the ads1147 and ads1148, there is a 100mv, and do not exceed avdd by more than multiplexer that selects the reference inputs, as 100mv, as shown in equation 2 . note that the same shown in figure 20 . the reference input uses a buffer caution is true if the inputs are configured to be to increase the input impedance. gpios. as with the analog inputs, refp0 and refn0 can be avss ? 100mv < (ainx) < avdd + 100mv (2) configured as digital i/os on the ads1147 and ads1148. settling time for channel multiplexing the ads1146/7/8 is a true single-cycle settling converter. the first data available after the start of a conversion are fully settled and valid for use. the time required to settle is roughly equal to the inverse of the data rate. the exact time depends on the specific data rate and the operation that resulted in the start of a conversion; see table 12 for specific values. analog input impedance the ads1146/7/8 inputs are buffered through a high- impedance pga before they reach the modulator. for the majority of applications, the input current leakage is minimal and can be neglected. however, because the pga is chopper-stabilized for noise and figure 20. reference input multiplexer offset performance, the input impedance is best described as a small absolute input current. the the reference input circuit has esd diodes to protect absolute current leakage for selected channels is the inputs. to prevent the diodes from turning on, approximately proportional to the selected modulator make sure the voltage on the reference input pin is clock. table 3 shows the typical values for these not less than avss ? 100mv, and does not exceed currents with a differential voltage coefficient and the avdd + 100mv, as shown in equation 3 : corresponding input impedances over data rate. avss ? 100mv < (v refp or v refn ) < avdd + 100mv (3) voltage reference input the voltage reference for the ads1146/7/8 is the differential voltage between refp and refn: table 3. typical values for analog input current over data rate effective input condition absolute input current impedance dr = 5sps, 10sps, 20sps (0.5na + 0.1na/v) 5000m dr = 40sps, 80sps, 160sps (2na + 0.5na/v) 1200m dr = 320sps, 640sps, 1ksps (4na + 1na/v) 600m dr = 2ksps (8na + 2na/v) 300m copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 19 product folder link(s): ads1146 ads1147 ads1148 refn1 refp1 adc ads1148 only refn0 refp0 v refn v refp vrefcom vrefout reference multiplexer internal voltage reference
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com low-noise pga the ads1146/7/8 feature a low-drift, low-noise, high (4) input impedance programmable gain amplifier (pga). the pga can be set to gain of 1, 2, 4, 8, 16, 32, 64, modulator or 128 by register sys0. a simplified diagram of the pga is shown in figure 21 . a third-order modulator is used in the ads1146/7/8. the modulator converts the analog input voltage into a pulse code modulated (pcm) data stream. to save power, the modulator clock runs from 32khz up to 512khz for different data rates, as shown in table 4 . digital filter the ads1146/7/8 use linear-phase finite impulse response (fir) digital filters that can be adjusted for different output data rates. the digital filter always settles in a single cycle. table 5 shows the exact data rates when an external oscillator equal to 4.096mhz is used. also shown is the signal ? 3db bandwidth, and the 50hz and 60hz attenuation. for good 50hz or 60hz rejection, use a data rate of 20sps or slower. the frequency responses of the digital filter are figure 21. simplified diagram of the pga shown in figure 22 to figure 32 . figure 25 shows a detailed view of the filter frequency response from 48hz to 62hz for a 20sps data rate. all filter plots the pga consists of two chopper-stabilized are generated with 4.096mhz external clock. amplifiers (a1 and a2) and a resistor feedback network that sets the gain of the pga. the pga input table 4. modulator clock frequency for different is equipped with an electromagnetic interference data rates (emi) filter, as shown in figure 21 . note that as with any pga, it is necessary to ensure that the input data rate f mod voltage stays within the specified common-mode (sps) (khz) input range specified in the electrical characteristics . 5, 10, 20 32 the common-mode input (v cmi ) must be within the 40, 80, 160 128 range shown in equation 4 : 320, 640, 1000 256 2000 512 table 5. digital filter specifications (1) attenuation data rate ? 3db bandwidth f in = 50hz 0.3hz f in = 60hz 0.3hz f in = 50hz 1hz f in = 60hz 1hz 5sps 2.26hz ? 106db ? 74db ? 81db ? 69db 10sps 4.76hz ? 106db ? 74db ? 80db ? 69db 20sps 14.8hz ? 71db ? 74db ? 66db ? 68db 40sps 9.03hz 80sps 19.8hz 160sps 118hz 320sps 154hz 640sps 495hz 1000sps 732hz 2000sps 1465hz (1) values shown for f osc = 4.096mhz. 20 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148 ( ) (v )(gain) in 2 avss + 0.1v + v cmi ( ) (v )(gain) in 2 avdd 0.1v - - adc a1 454 w 454 w 7.5pf a2 7.5pf 7.5pf 7.5pf rr c ain p ain n
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 figure 22. filter profile with data rate = 5sps figure 25. detailed view of filter profile with data rate = 20sps between 48hz and 62hz figure 23. filter profile with data rate = 10sps figure 26. filter profile with data rate = 40sps figure 24. filter profile with data rate = 20sps figure 27. filter profile with data rate = 80sps copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 21 product folder link(s): ads1146 ads1147 ads1148 50 52 54 56 58 60 - 60 - 70 - 80 - 90 - 100 - 110 - 120 48 frequency (hz) magnitude (db) 62 20 0 - 20 - 40 - 60 - 80 - 100 - 120 0 40 60 frequency (hz) magnitude (db) 80 100 120 140 160 180 200 200 0 - 20 - 40 - 60 - 80 - 100 - 120 0 400 600 frequency (hz) magnitude (db) 800 1000 1200 1400 1600 1800 2000 20 0 - 20 - 40 - 60 - 80 - 100 - 120 0 40 60 frequency (hz) magnitude (db) 80 100 120 140 160 180 200 200 0 - 20 - 40 - 60 - 80 - 100 - 120 0 400 600 frequency (hz) gain (db) 800 1000 1200 1400 1600 1800 2000 20 0 - 20 - 40 - 60 - 80 - 100 - 120 0 40 60 frequency (hz) magnitude (db) 80 100 120 140 160 180 200
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com figure 28. filter profile with data rate = 160sps figure 31. filter profile with data rate = 1ksps figure 29. filter profile with data rate = 320sps figure 32. filter profile with data rate = 2ksps clock source the ads1146/7/8 can use either the internal oscillator or an external clock. connect the clk pin to dgnd before power-on or reset to activate the internal oscillator. connecting an external clock to the clk pin at any time deactivates the internal oscillator, with the device then operating on the external clock. after the device switches to the external clock, it cannot be switched back to the internal oscillator without cycling the power supplies or resetting the device. figure 30. filter profile with data rate = 640sps 22 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148 200 0 - 20 - 40 - 60 - 80 - 100 - 120 0 400 600 frequency (hz) magnitude (db) 800 1000 1200 1400 1600 1800 2000 1 0 - 20 - 40 - 60 - 80 - 100 - 120 0 2 3 frequency (khz) magnitude (db) 4 5 6 7 8 9 10 500 0 - 20 - 40 - 60 - 80 - 100 - 120 0 1000 1500 frequency (hz) magnitude (db) 2000 2500 3000 3500 4000 4500 5000 2 0 - 20 - 40 - 60 - 80 - 100 - 120 0 4 6 frequency (khz) magnitude (db) 8 10 12 14 16 18 20 500 0 - 20 - 40 - 60 - 80 - 100 - 120 0 1000 1500 frequency (hz) magnitude (db) 2000 2500 3000 3500 4000 4500 5000
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 internal voltage reference the two matched current sources can be connected to dedicated current output pins iout1 and iout2 the ads1147 and ads1148 include an onboard (ads1148 only), or to any ain pin (ads1147 and voltage reference with a low temperature coefficient. ads1148); refer to the ads1147/48 detailed the output of the voltage reference is 2.048v with the register definitions section for more information. it is capability of both sourcing and sinking up to 10ma of possible to connect both current sources to the same current. pin. note that the internal reference must be turned on and properly compensated when using the the voltage reference must have a capacitor excitation current source dacs. connected between vrefout and vrefcom. the value of the capacitance should be in the range of 1 f to 47 f. large values provide more filtering of sensor detection the reference; however, the turn-on time increases the ads1146/7/8 provide a selectable current with capacitance, as shown in table 6 . for stability (0.5 a, 2 a, or 10 a) to help detect a possible reasons, vrefcom must have a path with an sensor malfunction. impedance less than 10 ? to ac ground nodes, such as gnd (for a 0v to 5v analog power supply), or when enabled, two burnout current sources flow avss for a 2.5v analog power supply). in case this through the selected pair of analog inputs to the impedance is higher than 10 ? , a capacitor of at least sensor. one sources the current to the positive input 0.1 f should be connected between vrefcom and channel, and the other sinks the same current from an ac ground node (for example, gnd). note that the negative input channel. because it takes time for the voltage reference to when the burnout current sources are enabled, a full- settle to the final voltage, care must be taken when scale reading may indicate an open circuit in the the device is turned off between conversions. allow front-end sensor, or that the sensor is overloaded. it adequate time for the internal reference to fully settle. may also indicate that the reference voltage is absent. a near-zero reading may indicate a short- table 6. internal reference settling time circuit in the sensor. vrefout settling time to reach the capacitor error settling error bias voltage generation 0.5% 70 s 1 f a selectable bias voltage is provided for use with 0.1% 110 s ungrounded thermocouples. the bias voltage is 0.5% 290 s (avdd + avss)/2 and can applied to any analog 4.7 f 0.1% 375 s input channel through internal input multiplexer. the 0.5% 2.2ms bias voltage turn-on times for different sensor 47 f capacitances are listed in table 7 . 0.1% 2.4ms the internal bias generator when selected on multiple the onboard reference is controlled by the registers; channels causes them to be internally shorted. by default, it is off after startup (see the ads1147/48 because of this, it is important that care be taken to detailed register definitions section for more details). limit the amount of current that may flow through the therefore, the internal reference must first be turned device. it is recommended that under no on and then connected via the internal reference circumstances more than 5ma be allowed to flow multiplexer. because the onboard reference is used through this path. this applies when the device is in to generate the current reference for the excitation operation and when it is in shutdown mode. current sources, it must be turned on before the excitation currents become available. table 7. bias voltage settling time sensor capacitance settling time excitation current source dacs 0.1 f 220 s the ads1147 and ads1148 provide two matched 1 f 2.2ms excitation current sources for rtd applications. for 10 f 22ms three- or four-wire rtd applications, the matched current sources can be used to cancel the errors 200 f 450ms caused by sensor lead resistance. the output current of the current source dacs can be programmed to 50 a, 100 a, 250 a, 500 a, 750 a, 1000 a, or 1500 a. copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 23 product folder link(s): ads1146 ads1147 ads1148
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com power-supply monitor general-purpose digital i/o the system monitor can measure the analog or the ads1148 has eight pins and the ads1147 has digital power supply. when measuring the power four pins that serve a dual purpose as either analog supply, the resulting conversion is approximately 1/4 inputs or general-purpose digital inputs/outputs of the actual power supply voltage. (gpios). conversion result = (v sp /4)/v ref (5) figure 33 shows a diagram of how these functions are combined onto a single pin. note that when the where v sp is the selected supply to be measured. pin is configured as a gpio, the corresponding logic is powered from avdd and avss. when the external voltage reference monitor ads1147 and ads1148 are operated with bipolar the ads1146/7/8 can be selected to measure the analog supplies, the gpio outputs bipolar voltages. external voltage reference. in this configuration, the care must be taken loading the gpio pins when monitored external voltage reference is connected to used as outputs because large currents can cause the analog input. the result (conversion code) is droop or noise on the analog supplies. approximately 1/4 of the actual reference voltage. conversion result = (v rex /4)/v ref (6) where v rex is the external reference to be monitored. note: the internal reference voltage must be enabled when measuring an external voltage reference using the system monitor. ambient temperature monitor on-chip diodes provide temperature-sensing capability. when selecting the temperature monitor function, the anodes of two diodes are connected to figure 33. analog/data interface pin the adc. typically, the difference in diode voltage is 118mv at +25 c with a temperature coefficient of 405 v/ c. system monitor note that when the onboard temperature monitor is the ads1147 and ads1148 provide a system selected, the pga is automatically set to '1'. monitor function. this function can measure the however, the pga register bits in are not affected analog power supply, digital power supply, external and the pga returns to its set value when the voltage reference, or ambient temperature. note that temperature monitor is turned off. the system monitor function provides a coarse result. when the system monitor is enabled, the analog inputs are disconnected. 24 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148 iocfg ainx/gpiox to analog mux dio write iodir dio read refx0/gpiox
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 calibration lsb correction and are used by the ads1146/7/8 calibration commands. if an ads1146/7/8 calibration the conversion data are scaled by offset and gain command is issued and the offset register is then registers before yielding the final output code. as read for storage and re-use later, it is recommended shown in figure 34 , the output of the digital filter is that all 24 bits of the ofc be used. when the first subtracted by the offset register (ofc) and then calibration commands are not used and the offset is multiplied by the full-scale register (fsc). a digital corrected by writing a user-calculated value to the clipping circuit ensures that the output code does not ofc register, it is recommended that only that only exceed 16 bits. equation 7 shows the scaling. ofc[2:1] be used and that ofc[0] be left as all zeros. note that while the offset calibration register value can correct offsets ranging from ? fs to +fs (as shown in table 8 ), make sure to avoid overloading the analog inputs. table 8. final output code versus offset calibration register setting figure 34. calibration block diagram final output code with offset register v in = 0 7fffffh 8000000h (7) 000001h ffffffh 000000h 000000h the values of the offset and full-scale registers are set by writing to them directly, or they are set ffffffh 000000h automatically by calibration commands. 8000000h 7fffffh the gain and offset calibration features are intended 1. excludes effects of noise and inherent offset for correction of minor system level offset and gain errors. errors. when entering manual values into the calibration registers, care must be taken to avoid full-scale calibration register: fsc[2:0] scaling down the gain register to values far below a the full-scale or gain calibration is a 24-bit word scaling facter of 1.0. under extreme situations it composed of three 8-bit registers. the full-scale becomes possible to over-range the adc. to avoid calibration value is 24-bit, straight binary, normalized this, make sure to avoid encountering situations to 1.0 at code 400000h. table 9 summarizes the where the analog inputs are connected to voltages scaling of the full-scale register. note that while the greater than the reference/pga. full-scale calibration register can correct gain errors care must also be taken when increasing the digital > 1 (with gain scaling < 1), make sure to avoid gain. when implementing custom digital gains less overloading the analog inputs. than 20% higher than nominal and offsets less than 40% of full scale, no special care is required. when table 9. gain correction factor versus full-scale operating at digital gains greater than 20% higher calibration register setting than nominal and offsets greater than 40% of full full-scale register gain scaling scale, make sure that the offset and gain registers 800000h 2.0 follow the conditions of equation 8. 400000h 1.0 200000h 0.5 (8) 000000h 0 offset calibration register: ofc[2:0] the offset calibration is a 24-bit word, composed of three 8-bit registers. the upper 16 bits, ofc[2:1], are the most important for calibration and can correct offsets ranging from ? fs to +fs, as shown in table 8 . the lower eight bits, ofc[0], provide sub- copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 25 product folder link(s): ads1146 ads1147 ads1148 adc s ofc register finaloutput output data clipped to 16 bits + - fsc register 400000h final output data = (input ofc[2:1]) - fsc[2:0] 400000h - 1.251v > |offset scaling| 2v gain scaling
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com calibration commands calibrations the offset calibration register (ofc) is updated afterwards. when either offset calibration the ads1146/7/8 provide commands for three types command is issued, the ads1146/7/8 stop the of calibration: system gain calibration, system offset current conversion and start the calibration procedure calibration and self offset calibration. where absolute immediately. accuracy is needed, it is recommended that calibration be performed after power on, a change in calibration timing temperature, a change of pga and in some cases a change in channel. at the completion of calibration, when calibration is initiated, the device performs 16 the drdy signal goes low indicating the calibration is consecutive data conversions and averages the finished. the first data after calibration are always results to calculate the calibration value. this valid. if the start pin is taken low or a sleep provides a more accurate calibration value. the time command is issued after any calibration command, required for calibration is shown in table 10 and can the devices goes to sleep after completing calibration. be calculated using equation 9 : it is important to allow a pending system calibration to complete before issuing any other commands. (9) issuing commands during a calibration can result in corrupted data. if this occurs either resend the table 10. calibration time versus data rate calibration command that was aborted or issue a data rate (sps) calibration time (ms) device reset. 5 3201.01 system gain calibration 10 1601.01 20 801.012 system gain calibration corrects for gain error in the 40 400.26 signal path. the system gain calibration is initiated by sending the sysgcal command while applying a 80 200.26 full-scale input to the selected analog inputs. 160 100.14 afterwards the full-scale calibration register (fsc) is 320 50.14 updated. when a system gain calibration command is 640 25.14 issued, the ads1146/7/8 stop the current conversion 1000 16.14 and start the calibration procedure immediately. 2000 8.07 system offset and self offset calibration 1. for f osc = 4.096mhz. system offset calibration corrects both internal and external offset errors. the system offset calibration is adc sleep mode initiated by sending the sysocal command while power consumption can be dramatically reduced by applying a zero differential input (v in = 0) to the placing the ads1146/7/8 into sleep mode. there are selected analog inputs. the self offset calibration is two ways to put the device into sleep mode: the sleep initiated by sending the selfocal command. command (sleep) and through the start pin. during self offset calibration, the selected inputs are disconnected from the internal circuitry and a zero during sleep mode, the internal reference status differential signal is applied internally. with both offset depends on the setting of the vrefcon bits in the mux1 register; see the register descriptions section for details. 26 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148 calibration time = 50 f osc 32 f mod 16 f data + +
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 adc control down to save power. during shutdown, the conversion result can be retrieved; however, start adc conversion control must be taken high before communicating with the configuration registers. the device stays shut down the start pin provides easy and precise control of until the start pin is once again taken high to begin conversions. pulse the start pin high to begin a a new conversion. when the start pin is taken conversion, as shown in figure 35 and table 11 . the back high again, the decimation filter is held in a conversion completion is indicated by the reset state for 32 modulator clock cycles internally to dout/ drdy pin going low. when the conversion allow the analog circuits to settle. completes, the ads1146/7/8 automatically shuts figure 35. timing for single conversion using start pin table 11. start pin conversion times for figure 35 symbol description data rate (sps) value unit 5 200.295 ms 10 100.644 ms 20 50.825 ms 40 25.169 ms 80 12.716 ms time from start pulse to drdy and t conv dout/ drdy going low 160 6.489 ms 320 3.247 ms 640 1.692 ms 1000 1.138 ms 2000 0.575 ms copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 27 product folder link(s): ads1146 ads1147 ads1148 converting start dout/drdy sclk drdy ads1146/7/8 status shutdown 1 2 3 16 t conv t start
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com the ads1146/7/8 can be configured to convert transferred to the ads1146/7/8, new settings become continuously by holding the start pin high, as active at the end of each byte sent. therefore, a brief shown in figure 36 . with the start pin held high, overload condition can occur during the transmission the adc converts the selected input channels of configuration data after the completion of the continuously. this configuration continues until the mux0 byte and before the completion of the sys0 start pin is taken low. byte. this temporary overload can result in intermittent incorrect readings. to ensure that an the start pin can also be used to perform the overload does not occur, it may be necessary to split synchronized measurement for the multi-channel the communication into two separate communications applications by pulsing the start pin. allowing the change of the sys0 register bfore the change of the mux0 register. reset in the event of an overloaded state, care must also when the reset pin goes low, the device is be taken to ensure single cycle settling into the next immediately reset. all the registers are restored to cycle. because the ads1146/7/8 implement a default values. the device stays in reset mode as chopper-stabilized pga, changing data rates during long as the reset pin stays low. when it goes high, an overload state can cause the chopper to become the adc comes out of reset mode and is able to unstable. this instability results in slow settling time. convert data. after the reset pin goes high, and to prvent this slow settling, always change the pga when the system clock frequency is 4.096mhz, the setting or mux setting to a non-overloaded state digital filter and the registers are held in a reset state bfore changing the data rate. for 0.6ms when f osc = 4.096mhz. therefore, valid spi communication can only be resumed 0.6ms after single-cycle settling the reset pin goes high; see figure 4 . when the reset pin goes low, the clock selection is reset to the ads1146/7/8 are capable of single-cycle settling the internal oscillator. across all gains and data rates. however, to achieve single-cycle settling at 2ksps, special care must be channel cycling and overload recovery taken with respect to the interface. when operating at 2ksps, the spi data sclk period must not exceed when cycling through channels, care must be taken 520ns, and the time between the beginning of a byte when configuring the ads1146/7/8 to ensure that and the beginning of a subsequent byte must not settling occurs within one cycle. for setups that exceed 4.2 s. additionally, when performing multiple simply cycle through mux channels, but do not individual write commands to the first four registers, change pga and data rate settings, simply changing wait at least 64 oscillator clocks before initiating the mux0 register is sufficient. however, when another write command. changing pga and data rate settings it is important to ensure that an overloaded condition cannot occur during the transmission. when configuration data are note: sclk held low in this example. figure 36. timing for conversion with start pin high 28 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148 converting converting converting converting start dout/drdy ads1146/7/8 status data ready data ready data ready
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 digital filter reset operation takes place in the vbias, mux1, or sys0 registers, the filter is reset as well, regardless of whether the apart from the reset command and the reset pin, value changed or not. the reset pulse lasts for 32 the digital filter is reset automatically when either a modulator clocks after the write operation. if there are write operation to the mux0, vbias, mux1, or sys0 multiple write operations, the resulting reset pulse registers is performed, when a sync command is may be viewed as the anded result of the different issued, or the start pin is taken high. active low pulses created individually by each action. the filter is reset two system clocks after the last bit table 12 shows the conversion time after a filter of the sync command is sent. the reset pulse reset. note that this time depends on the operation created internally lasts for two multiplier clock cycles. initiating the reset. also, the first conversion after a if any write operation takes place in the mux0 filter reset has a slightly different time than the register, the filter is reset regardless of whether the second and subsequent conversions. value changed or not. internally, the filter pulse lasts for two system clock periods. if any write activity table 12. data conversion time first data conversion time after filter reset hardware reset, reset command, start pin high, wakeup command, vbias, second and subsequent sync command, mux0 mux1, or sys0 register conversion time after register write write filter reset no. of no. of no. of nominal exact data system system system data rate rate clock clock clock (sps) (sps) (ms) (1) cycles (ms) (1) cycles (ms) cycles 5 5.019 199.258 816160 200.26 820265 199.250 816128 10 10.038 99.633 408096 100.635 412201 99.625 408064 20 20.075 49.820 204064 50.822 208169 49.812 204032 40 40.151 24.920 102072 25.172 103106 24.906 102016 80 80.301 12.467 51064 12.719 52098 12.453 51008 160 160.602 6.241 25560 6.492 26594 6.226 25504 320 321.608 3.124 12796 3.250 13314 3.109 12736 640 643.216 1.569 6428 1.695 6946 1.554 6368 1000 1000.000 1.014 4156 1.141 4674 1.000 4096 2000 2000.000 0.514 2108 0.578 2370 0.500 2048 (1) for f osc = 4.096mhz. copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 29 product folder link(s): ads1146 ads1147 ads1148
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com data format the ads1146/7/8 implement a timout function for all listed commands in the event that data is corrupted the ads1146/7/8 output 16 bits of data in binary and chip select is permanently tied low. however, it is twos complement format. the least significant bit important in systems where chip select is tied low (lsb) has a weight of (v ref /pga)/(2 15 ? 1). the permanently that register writes always be fully positive full-scale input produces an output code of completed in 8 bit increments. the sclk line should 7fffh and the negative full-scale input produces an also be kept clean and situations should be avoided output code of 8000h. the output clips at these codes where noise on the sclk line could cause the device for signals exceeding full-scale. table 13 summarizes to interpret the transient as a false sclk pulse. in the ideal output codes for different input signals. systems where such events are likely to occur, it is recommended that chip select be used to frame table 13. ideal output code vs input signal communications to the device. input signal, v in sclk (ain p ? ain n ) ideal output code this signal is the serial clock signal. sclk provides +v ref /pga 7fffh the clock for serial communication. it is a schmitt- (+v ref /pga)/(2 15 ? 1) 0001h trigger input, but it is highly recommended that sclk 0 0000h be kept as clean as possible to prevent glitches from ( ? v ref /pga)/(2 15 ? 1) ffffh inadvertently shifting the data. data are shifted into din on the falling edge of sclk and shifted out of ? (v ref /pga) (2 15 /2 15 ? 1) 8000h dout on the rising edge of sclk. 1. excludes effects of noise, linearity, offset, and din gain errors. this pin is the data input pin. din is used along with sclk to send data to the device. data on din are digital interface shifted into the device on the falling edge of sclk. the ads1146/7/8 provide a standard spi serial the communication of this device is full-duplex in communication interface plus a data ready signal nature. the device monitors commands shifted in ( drdy). communication is full-duplex with the even when data are being shifted out. data that are exception of a few limitations in regards to the rreg present in the output shift register are shifted out command and the rdata command. these when sending in a command. therefore, it is limitations are explained in detail in the spi important to make sure that whatever is being sent on commands section of this data sheet. for the basic the din pin is valid when shifting out data. when no serial interface timing characteristics, see figure 1 command is to be sent to the device when reading and figure 2 of this document. out data, the nop command should be sent on din. cs drdy this pin is the chip select pin (active low). the cs pin this pin is the data ready pin. the drdy pin goes activates spi communication. cs must be low before low to indicate a new conversion is complete, and the data transactions and must stay low for the entire spi conversion result is stored in the conversion result communication period. when cs is high, the buffer. the spi clock must be low in a short time dout/ drdy pin enters a high-impedance state. frame around the drdy low transition (see figure 2 ) therefore, reading and writing to the serial interface so that the conversion result is loaded into both the are ignored and the serial interface is reset. drdy result buffer and the output shift register. therefore, pin operation is independent of cs. no commands should be issued during this time taking cs high deactivates only the spi frame if the conversion result is to be read out later. communication with the device. data conversion this constraint applies only when cs is asserted. continues and the drdy signal can be monitored to when cs is not asserted, spi communication with check if a new conversion result is ready. a master other devices on the spi bus does not affect loading device monitoring the drdy signal can select the of the conversion result. after the drdy pin goes appropriate slave device by pulling the cs pin low. low, it is forced high on the first falling edge of sclk (so that the drdy pin can be polled for '0' instead of waiting for a falling edge). if the drdy pin is not taken high after it falls low, a short high pulse is created on it to indicate the next data are ready. 30 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 dout/ drdy by providing 16 sclks. in order to force this pin has two modes: data out (dout) only, or dout/ drdy high (so that dout/ drdy can be data out (dout) combined with data ready ( drdy). polled for a '0' instead of waiting for a falling edge), a the drdy mode bit determines the function of this no operation command (nop) or any other command pin. in either mode, the dout/ drdy pin goes to a that does not load the data output register can be high-impedance state when cs is taken high. sent after reading out the data. because sclks can only be sent in multiples of eight, a nop can be sent when the drdy mode bit is set to '0', this pin to force dout/ drdy high if no other command is functions as dout only. data are clocked out at pending. the dout/ drdy pin goes high after the rising edge of sclk, msb first, as shown in first rising edge of sclk after reading the conversion figure 37 . result completely (see figure 39 ). the same condition also applies after an rreg command. after all the when the drdy mode bit is set to '1', this pin register bits have been read out, the rising edge of functions as both dout and drdy. data are shifted sclk forces dout/ drdy high. figure 40 illustrates out from this pin, msb first, at the rising edge of an example where sending four nop commands after sclk. this combined pin allows for the same control an rreg command forces the dout/ drdy pin but with fewer pins. high. when the drdy mode bit is enabled and a new the drdy mode bit modifies only the dout/ drdy conversion is complete, dout/ drdy goes low if it is pin functionality. the drdy pin functionality remains high. if it is already low, then dout/ drdy goes high unaffected. and then goes low, as shown in figure 38 . similar to the drdy pin, a falling edge on the dout/ drdy pin signals that a new conversion result is ready. after dout/ drdy goes low, the data can be clocked out (1) cs tied low. figure 37. data retrieval with the drdy mode bit = 0 (disabled) (1) cs tied low. figure 38. data retrieval with the drdy mode bit = 1 (enabled) copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 31 product folder link(s): ads1146 ads1147 ads1148 sclk d[15] 1 2 14 1 2 8 15 16 3 d[14] d[13] d[2] d[1] d[0] dout/ (1) drdy drdy sclk din 1 1 d[15] d[14] d[15] d[14] d[13] nop nop d[2] d[1] d[0] d[0] 2 2 3 14 15 16 16 dout/ (1) drdy drdy
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com (1) drdy mode bit enabled, cs tied low. figure 39. dout/ drdy forced high after retrieving the conversion result (1) drdy mode bit enabled, cs tied low. figure 40. dout/ drdy forced high after reading register data spi reset spi communication during sleep mode spi communication can be reset in several ways. in when the start pin is low or the device is in sleep order to reset the spi interface (without resetting the mode, only the rdata, rdatac, sdatac, registers or the digital filter), the cs pin can be pulled wakeup, and nop commands can be issued. the high. taking the reset pin low causes the spi rdata command can be used to repeatedly read the interface to be reset along with all the other digital last conversion result during sleep mode. other functions. in this case, the registers and the commands do not function because the internal clock conversion are reset. is shut down to save power during sleep mode. 32 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148 sclk din 1 1 d[15] d[14] d[15] d[14] d[13] nop nop nop d[2] d[1] d[0] d[0] 2 2 3 14 15 16 1 2 8 16 dout/ (1) drdy drdy sclk dout/ (1) drdy din nop 1 reg[7] reg[1] reg[0] 2 1 2 7 8 7 8 nop
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 register descriptions ads1146 register map table 14. ads1146 register map address register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h bcs bcs1 bcs0 0 0 0 0 0 1 01h vbias 0 0 0 0 0 0 vbias1 vbias0 02h mux1 clkstat 0 0 0 0 muxcal2 muxcal1 muxcal0 03h sys0 0 pga2 pga1 pga0 dr3 dr2 dr1 dr0 04h ofc0 ofc7 ofc6 ofc5 ofc4 ofc3 ofc2 ofc1 ofc0 05h ofc1 ofc15 ofc14 ofc13 ofc12 ofc11 ofc10 ofc9 ofc8 06h ofc2 ofc23 ofc22 ofc21 ofc20 ofc19 ofc18 ofc17 ofc16 07h fsc0 fsc7 fsc6 fsc5 fsc4 fsc3 fsc2 fsc1 fsc0 08h fsc1 fsc15 fsc14 fsc13 fsc12 fsc11 fsc10 fsc9 fsc8 09h fsc2 fsc23 fsc22 fsc21 fsc20 fsc19 fsc18 fsc17 fsc16 drdy 0ah id id3 id2 id1 id0 0 0 0 mode ads1146 detailed register definitions bcs ? burnout current source register. these bits control the settling of the sensor burnout detect current source. bcs - address 00h reset value = 01h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bcs1 bcs0 0 0 0 0 0 1 bits[7:6] bcs[1:0] these bits select the magnitude of the sensor burnout detect current source. 00 = burnout current source off (default) 01 = burnout current source on, 0.5 a 10 = burnout current source on, 2 a 11 = burnout current source on, 10 a bits[5:0] these bits must always be set to '000001'. copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 33 product folder link(s): ads1146 ads1147 ads1148
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com ads1146 detailed register definitions (continued) vbias ? bias voltage register. this register enables a bias voltage on the analog inputs. vbias - address 01h reset value = 00h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 0 0 vbias1 vbias0 bits[7:2] these bits must always be set to '000000'. bits[1:0] vbias[1:0] these bits apply a bias voltage of midsupply (avdd + avss)/2 to the selected analog input. bit 0 is for ain0, and bit 1 is for ain1. 0 = bias voltage not enabled (default) 1 = bias voltage is applied to the analog input mux ? multiplexer control register. mux - address 02h reset value = x0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 clkstat 0 0 0 0 muxcal2 muxcal1 muxcal0 bit 7 clkstat this bit is read-only and indicates whether the internal or external oscillator is being used. 0 = internal oscillator in use 1 = external oscillator in use bits[6:3] these bits must always be set to '0000'. bits[2:0] muxcal[2:0] these bits are used to select a system monitor. the muxcal selection supercedes selections from the vbias register. 000 = normal operation (default) 001 = offset calibration. the analog inputs are disconnected and ainp and ainn are internally connected to midsupply (avdd + avss)/2. 010 = gain calibration. the analog inputs are connected to the voltage reference. 011 = temperature measurement. the inputs are connected to a diode circuit that produces a voltage proportional to the ambient temperature of the device. table 15 lists the adc input connection and pga settings for each muxcal setting. the pga setting reverts to the original sys0 register setting when muxcal is taken back to normal operation or offset measurement. table 15. muxcal settings muxcal[2:0] pga gain setting adc input 000 set by sys0 register normal operation 001 set by sys0 register offset calibration: inputs shorted to midsupply (avdd + avss)/2 010 forced to 1 gain calibration: v refp ? v refn (full-scale) 011 forced to 1 temperature measurement diode 34 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 ads1146 detailed register definitions (continued) sys0 ? system control register 0. sys0 - address 03h reset value = 00h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 pga2 pga1 pga0 dor3 dor2 dor1 dor0 bit 7 these bits must always be set to '0'. bits[6:4] pga[2:0] these bits determine the gain of the pga. 000 = 1 (default) 001 = 2 010 = 4 011 = 8 100 = 16 101 = 32 110 = 64 111 = 128 bits[3:0] dor[3:0] these bits select the output data rate of the adc. bits with a value higher than 1001 select the highest data rate of 2000sps. 0000 = 5sps (default) 0001 = 10sps 0010 = 20sps 0011 = 40sps 0100 = 80sps 0101 = 160sps 0110 = 320sps 0111 = 640sps 1000 = 1000sps 1001 to 1111 = 2000sps ofc[23:0] these bits make up the offset calibration coefficient register of the ads1148. ofc0 ? offset calibration coefficient register 0 ofc0 - address 04h reset value = 00h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ofc7 ofc6 ofc5 ofc4 ofc3 ofc2 ofc1 ofc0 ofc1 ? offset calibration coefficient register 1 ofc1 - address 05h reset value = 00h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ofc15 ofc14 ofc13 ofc12 ofc11 ofc10 ofc9 ofc8 ofc2 ? offset calibration coefficient register 2 ofc2 - address 06h reset value = 00h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ofc23 ofc22 ofc21 ofc20 ofc19 ofc18 ofc17 ofc16 copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 35 product folder link(s): ads1146 ads1147 ads1148
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com ads1146 detailed register definitions (continued) fsc[23:0] these bits make up the full-scale calibration coefficient register. fsc0 ? full-scale calibration coefficient register 0 fsc0 - address 07h reset value is pga dependent (1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fsc7 fsc6 fsc5 fsc4 fsc3 fsc2 fsc1 fsc0 (1) the reset value for fsc is factory-trimmed for each pga setting. note that the factory-trimmed fsc reset value is automatically loaded whenever the pga setting is changed. fsc1 ? full-scale calibration coefficient register 1 fsc1 - address 08h reset value is pga dependent (1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fsc15 fsc14 fsc13 fsc12 fsc11 fsc10 fsc9 fsc8 (1) the reset value for fsc is factory-trimmed for each pga setting. note that the factory-trimmed fsc reset value is automatically loaded whenever the pga setting is changed. fsc2 ? full-scale calibration coefficient register 2 fsc2 - address 09h reset value is pga dependent (1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fsc23 fsc22 fsc21 fsc20 fsc19 fsc18 fsc17 fsc16 (1) the reset value for fsc is factory-trimmed for each pga setting. note that the factory-trimmed fsc reset value is automatically loaded whenever the pga setting is changed. id ? id register idac0 - address 0ah reset value = x0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 id3 id2 id1 id0 drdy mode 0 0 0 bits 7:4 id3:0 read-only, factory-programmed bits; used for revision identification. bit 3 drdy mode this bit sets the dout/ drdy pin functionality. in either setting of the drdy mode bit, the drdy pin continues to indicate data ready, active low. 0 = dout/ drdy pin functions only as data out (default) 1 = dout/ drdy pin functions both as data out and data ready, active low bits 2:0 these bits must always be set to '000'. 36 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 ads1147 and ads1148 register map table 16. ads1147 and ads1148 register map address register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h mux0 bcs1 bcs0 mux_sp2 mux_sp1 mux_sp0 mux_sn2 mux_sn1 mux_sn0 01h vbias vbias7 vbias6 vbias5 vbias4 vbias3 vbias2 vbias1 vbias0 02h mux1 clkstat vrefcon1 vrefcon0 refselt1 refselt0 muxcal2 muxcal1 muxcal0 03h sys0 0 pga2 pga1 pga0 dr3 dr2 dr1 dr0 04h ofc0 ofc7 ofc6 ofc5 ofc4 ofc3 ofc2 ofc1 ofc0 05h ofc1 ofc15 ofc14 ofc13 ofc12 ofc11 ofc10 ofc9 ofc8 06h ofc2 ofc23 ofc22 ofc21 ofc20 ofc19 ofc18 ofc17 ofc16 07h fsc0 fsc7 fsc6 fsc5 fsc4 fsc3 fsc2 fsc1 fsc0 08h fsc1 fsc15 fsc14 fsc13 fsc12 fsc11 fsc10 fsc9 fsc8 09h fsc2 fsc23 fsc22 fsc21 fsc20 fsc19 fsc18 fsc17 fsc16 drdy 0ah idac0 id3 id2 id1 id0 imag2 imag1 imag0 mode 0bh idac1 i1dir3 i1dir2 i1dir1 i1dir0 i2dir3 i2dir2 i2dir1 i2dir0 0ch gpiocfg iocfg7 iocfg6 iocfg5 iocfg4 iocfg3 iocfg2 iocfg1 iocfg0 0dh gpiodir iodir7 iodir6 iodir5 iodir4 iodir3 iodir2 iodir1 iodir0 0eh gpiodat iodat7 iodat6 iodat5 iodat4 iodat3 iodat2 iodat1 iodat0 copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 37 product folder link(s): ads1146 ads1147 ads1148
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com ads1147 and ads1148 detailed register definitions mux0 ? multiplexer control register 0. this register allows any combination of differential inputs to be selected on any of the input channels. note that this setting can be superceded by the muxcal and vbias bits. mux0 - address 00h reset value = 01h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bcs1 bcs0 mux_sp2 mux_sp1 mux_sp0 mux_sn2 mux_sn1 mux_sn0 bits[7:6] bcs[1:0] these bits select the magnitude of the sensor detect current source. 00 = burnout current source off (default) 01 = burnout current source on, 0.5 a 10 = burnout current source on, 2 a 11 = burnout current source on, 10 a bits[5:3] mux_sp[2:0] positive input channel selection bits. 000 = ain0 (default) 001 = ain1 010 = ain2 011 = ain3 100 = ain4 (ads1148 only) 101 = ain5 (ads1148 only) 110 = ain6 (ads1148 only) 111 = ain7 (ads1148 only) bits[2:0] mux_sn[2:0] negative input channel selection bits. 000 = ain0 001 = ain1 (default) 010 = ain2 011 = ain3 100 = ain4 (ads1148 only) 101 = ain5 (ads1148 only) 110 = ain6 (ads1148 only) 111 = ain7 (ads1148 only) vbias ? bias voltage register vbias - address 01h reset value = 00h device bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ads1148 vbias7 vbias6 vbias5 vbias4 vbias3 vbias2 vbias1 vbias0 ads1147 0 0 0 0 vbias3 vbias2 vbias1 vbias0 bits[7:0] vbias[7:0] these bits apply a bias voltage of midsupply (avdd + avss)/2 to the selected analog input. 0 = bias voltage not enabled (default) 1 = bias voltage is applied on the corresponding analog input (bit 0 corresponds to ain0, etc.). 38 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 ads1147 and ads1148 detailed register definitions (continued) mux1 ? multiplexer control register 1 mux1 - address 02h reset value = 00h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 clkstat vrefcon1 vrefcon0 refselt1 refselt0 muxcal2 muxcal1 muxcal0 bit 7 clkstat this bit is read-only and indicates whether the internal or external oscillator is being used. 0 = internal oscillator in use 1 = external oscillator in use bits[6:5] vrefcon[1:0] these bits control the internal voltage reference. these bits allow the reference to be turned on or off completely, or allow the reference state to follow the state of the device. note that the internal reference is required for operation of the idac functions. 00 = internal reference is always off (default) 01 = internal reference is always on 10 or 11 = internal reference is on when a conversion is in progress and shuts down when the device receives a shutdown opcode or the start pin is taken low bits[4:3] refselt[1:0] these bits select the reference input for the adc. 00 = ref0 input pair selected (default) 01 = ref1 input pair selected (ads1148 only) 10 = onboard reference selected 11 = onboard reference selected and internally connected to ref0 input pair bits[2:0] muxcal[2:0] these bits are used to select a system monitor. the muxcal selection supercedes selections from registers mux0 and mux1 (mux_sp, mux_sn, and vbias). 000 = normal operation (default) 001 = offset measurement 010 = gain measurement 011 = temperature diode 100 = external ref1 measurement (ads1148 only) 101 = external ref0 measurement 110 = avdd measurement 111 = dvdd measurement table 17 provides the adc input connection and pga settings for each muxcal setting. the pga setting reverts to the original sys0 register setting when muxcal is taken back to normal operation or offset measurement. table 17. muxcal settings muxcal[2:0] pga gain setting adc input 000 set by sys0 register normal operation 001 set by sys0 register inputs shorted to midsupply (avdd + avss)/2 010 forced to 1 v refp ? v refn (full-scale) 011 forced to 1 temperature measurement diode 100 forced to 1 (v refp1 ? v refn1 )/4 101 forced to 1 (v refp0 ? v refn0 )/4 110 forced to 1 (avdd ? avss)/4 111 forced to 1 (dvdd ? dvss)/4 copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 39 product folder link(s): ads1146 ads1147 ads1148
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com ads1147 and ads1148 detailed register definitions (continued) sys0 ? system control register 0 sys0 - address 03h reset value = 00h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 pga2 pga1 pga0 dor3 dor2 dor1 dor0 bit 7 this bit must always be set to '0' bits[6:4] pga[2:0] these bits determine the gain of the pga. 000 = 1 (default) 001 = 2 010 = 4 011 = 8 100 = 16 101 = 32 110 = 64 111 = 128 bits[3:0] dor[3:0] these bits select the output data rate of the adc. bits with a value higher than 1001 select the highest data rate of 2000sps. 0000 = 5sps (default) 0001 = 10sps 0010 = 20sps 0011 = 40sps 0100 = 80sps 0101 = 160sps 0110 = 320sps 0111 = 640sps 1000 = 1000sps 1001 to 1111 = 2000sps ofc[23:0] these bits make up the offset calibration coefficient register of the ads1148. ofc0 ? offset calibration coefficient register 0 ofc0 - address 04h reset value = 000000h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ofc7 ofc6 ofc5 ofc4 ofc3 ofc2 ofc1 ofc0 ofc1 ? offset calibration coefficient register 1 ofc1 - address 05h reset value = 000000h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ofc15 ofc14 ofc13 ofc12 ofc11 ofc10 ofc9 ofc8 ofc2 ? offset calibration coefficient register 2 ofc2 - address 06h reset value = 000000h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ofc23 ofc22 ofc21 ofc20 ofc19 ofc18 ofc17 ofc16 40 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 ads1147 and ads1148 detailed register definitions (continued) fsc[23:0] these bits make up the full-scale calibration coefficient register. fsc0 ? full-scale calibration coefficient register 0 fsc0 - address 07h reset value is pga dependent (1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fsc7 fsc6 fsc5 fsc4 fsc3 fsc2 fsc1 fsc0 (1) the reset value for fsc is factory-trimmed for each pga setting. note that the factory-trimmed fsc reset value is automatically loaded whenever the pga setting is changed. fsc1 ? full-scale calibration coefficient register 1 fsc1 - address 08h reset value is pga dependent (1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fsc15 fsc14 fsc13 fsc12 fsc11 fsc10 fsc9 fsc8 (1) the reset value for fsc is factory-trimmed for each pga setting. note that the factory-trimmed fsc reset value is automatically loaded whenever the pga setting is changed. fsc2 ? full-scale calibration coefficient register 2 fsc2 - address 09h reset value is pga dependent (1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fsc23 fsc22 fsc21 fsc20 fsc19 fsc18 fsc17 fsc16 (1) the reset value for fsc is factory-trimmed for each pga setting. note that the factory-trimmed fsc reset value is automatically loaded whenever the pga setting is changed. idac0 ? idac control register 0 idac0 - address 0ah reset value = x0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 id3 id2 id1 id0 drdy mode imag2 imag1 imag0 bits[7:4] id[3:0] read-only, factory-programmed bits; used for revision identification. bit 3 drdy mode this bit sets the dout/ drdy pin functionality. in either setting of the drdy mode bit, the drdy pin continues to indicate data ready, active low. 0 = dout/ drdy pin functions only as data out (default) 1 = dout/ drdy pin functions both as data out and data ready, active low bits[2:0] imag[2:0] the ads1147 and ads1148 have two programmable current source dacs that can be used for sensor excitation. the imag bits control the magnitude of the excitation current. the idacs require the internal reference to be on. 000 = off (default) 001 = 50 a 010 = 100 a 011 = 250 a 100 = 500 a 101 = 750 a 110 = 1000 a 111 = 1500 a copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 41 product folder link(s): ads1146 ads1147 ads1148
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com ads1147 and ads1148 detailed register definitions (continued) idac1 ? idac control register 1 idac1 - address 0bh reset value = ffh device bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ads1148 i1dir3 i1dir2 i1dir1 i1dir0 i2dir3 i2dir2 i2dir1 i2dir0 ads1147 0 0 i1dir1 i1dir0 0 0 i2dir1 i2dir0 the two idacs on the ads1147 and ads1148 can be routed to either the iexc1 and iexc2 output pins or directly to the analog inputs. bits[7:4] i1dir[3:0] these bits select the output pin for the first current source dac. 0000 = ain0 0001 = ain1 0010 = ain2 0011 = ain3 0100 = ain4 (ads1148 only) 0101 = ain5 (ads1148 only) 0110 = ain6 (ads1148 only) 0111 = ain7 (ads1148 only) 10x0 = iext1 (ads1148 only) 10x1 = iext2 (ads1148 only) 11xx = disconnected (default) bits[3:0] i2dir[3:0] these bits select the output pin for the second current source dac. 0000 = ain0 0001 = ain1 0010 = ain2 0011 = ain3 0100 = ain4 (ads1148 only) 0101 = ain5 (ads1148 only) 0110 = ain6 (ads1148 only) 0111 = ain7 (ads1148 only) 10x0 = iext1 (ads1148 only) 10x1 = iext2 (ads1148 only) 11xx = disconnected (default) 42 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 ads1147 and ads1148 detailed register definitions (continued) gpiocfg ? gpio configuration register. the gpio and analog pins are shared as follows: gpio0 shared with refp0 gpio1 shared with refn0 gpio2 shared with ain2 gpio3 shared with ain3 gpio4 shared with ain4 (ads1148) gpio5 shared with ain5 (ads1148) gpio6 shared with ain6 (ads1148) gpio7 shared with ain7 (ads1148) gpiocfg - address 0ch reset value = 00h device bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ads1148 iocfg7 iocfg6 iocfg5 iocfg4 iocfg3 iocfg2 iocfg1 iocfg0 ads1147 0 0 0 0 iocfg3 iocfg2 iocfg1 iocfg0 bits[7:0] iocfg[7:0] these bits enable the gpio because the gpio pins are shared with the analog pins. note that the ads1148 uses all the iocfg bits, whereas the ads1147 uses only bits 3:0. 0 = the pin is used as an analog input (default) 1 = the pin is used as a gpio pin gpiodir ? gpio direction register gpiodir - address 0dh reset value = 00h device bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ads1148 iodir7 iodir6 iodir5 iodir4 iodir3 iodir2 iodir1 iodir0 ads1147 0 0 0 0 iodir3 iodir2 iodir1 iodir0 bits[7:0] iodir[7:0] these bits control the direction of the gpio when enabled by the iocfg bits. note that the ads1148 uses all the iodir bits, whereas the ads1147 uses only bits 3:0. 0 = the gpio is an output (default) 1 = the gpio is an input gpiodat ? gpio data register gpiodat - address 0eh reset value = 00h device bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ads1148 iodat7 iodat6 iodat5 iodat4 iodat3 iodat2 iodat1 iodat0 ads1147 0 0 0 0 iodat3 iodat2 iodat1 iodat0 bits[7:0] iodat[7:0] if a gpio pin is enabled in the gpiocfg register and configured as an output in the gpio direction register (gpiodir), the value written to this register appears on the appropriate gpio pin. if a gpio pin is configured as an input in gpiodir, reading this register returns the value of the digital i/o pins. note that the ads1148 uses all eight iodat bits, while the ads1147 uses only bits 3:0. copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 43 product folder link(s): ads1146 ads1147 ads1148
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com spi commands spi command definitions the commands shown in table 18 control the operation of the ads1146/7/8. some of the commands are stand- alone commands (for example, reset), whereas others require additional bytes (for example, wreg requires command, count, and the data bytes). operands: n = number of registers to be read or written (number of bytes ? 1) r = register (0 to 15) x = don't care table 18. spi commands command type command description 1st command byte 2nd command byte wakeup exit sleep mode 0000 000x (00h, 01h) sleep enter sleep mode 0000 001x (02h, 03h) system control sync synchronize the a/d conversion 0000 010x (04h, 05h) 0000-010x (04,05h) reset reset to power-up values 0000 011x (06h, 07h) nop no operation 1111 1111 (ffh) rdata read data once 0001 001x (12h, 13h) data read rdatac read data continuously 0001 010x (14h, 15h) sdatac stop reading data continuously 0001 011x (16h, 17h) read register rreg read from register rrrr 0010 rrrr (2xh) 0000_nnnn write register wreg write to register rrrr 0100 rrrr (4xh) 0000_nnnn sysocal system offset calibration 0110 0000 (60h) calibration sysgcal system gain calibration 0110 0001 (61h) selfocal self offset calibration 0110 0010 (62h) restricted command. restricted 1111 0001 (f1h) should never be sent to device. 44 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 system control commands wakeup ? wake up from sleep mode that is set by the sleep command. use this command to awaken the device from sleep mode. after execution of the wakeup command, the device wakes up on the rising edge of the eighth sclk. sleep ? set the device to sleep mode; issue the wakeup command to deactivate sleep mode. this command places the part into a sleep (power-saving) mode. when the sleep command is issued, the device completes the current conversion and then goes into sleep mode. note that this command does not automatically power-down the internal voltage reference; see the vrefcon bits in the mux1 register for each device for further details. to exit sleep mode, issue the wakeup command. single conversions can be performed by issuing a wakeup command followed by a sleep command. both wakeup and sleep are the software command equivalents of using the start pin to control the device. figure 41. sleep and wakeup commands operation sync ? synchronize drdy. this command resets the adc digital filter and starts a new conversion. the drdy pin from multiple devices connected to the same spi bus can be synchronized by issuing a sync command to all of devices simultaneously. figure 42. sync command operation reset ? reset the device to power-up state. this command restores the registers to the respective power-up values. this command also resets the digital filter. reset is the command equivalent of using the reset pin to reset the device. however, the reset command does not reset the spi interface. if the reset command is issued when the spi interface is in the wrong state, the device will not reset. the cs pin can be used to reset spi interface first, and then a reset command can be issued to reset the device. the reset command holds the registers and the decimation filter in a reset state for 0.6ms when the system clock frequency is 4.096mhz, similar to the hardware reset. therefore, spi communication can be only be started 0.6ms after the reset command is issued, as shown in figure 43 . figure 43. spi communication after an spi reset copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 45 product folder link(s): ads1146 ads1147 ads1148 synchronizationoccurs here 2 t osc sync din sclk 0000 010x 0000 010x sclk reset 1 8 any spi command din 0.6ms din sclk drdy status sleep normal mode sleep mode finish current conversion normal mode start new conversion eighth sclk wakeup 0000 001x 0000 000x
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com data retrieval commands rdatac ? read data continuously. the rdatac command enables the automatic loading of a new conversion result into the output data register. in this mode, the conversion result can be received once from the device after the drdy signal goes low by sending 16 sclks. it is not necessary to read back all the bits, as long as the number of bits read out is a multiple of eight. the rdatac command must be issued after drdy goes low, and the command takes effect on the next drdy. be sure to complete data retrieval (conversion result or register read-back) before drdy goes low, or the resulting data will be corrupt. successful register read operations in rdatac mode require the knowledge of when the next drdy falling edge will occur. figure 44. read data continuously sdatac ? stop reading data continuously. the sdatac command terminates the rdatac mode. afterwards, the conversion result is not automatically loaded into the output shift register when drdy goes low, and register read operations can be performed without interruption from new conversion results being loaded into the output shift register. use the rdata command to retrieve conversion data. the sdatac command takes effect after the next drdy. figure 45. stop reading data continuously 46 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148 din dout drdy rdatac sclk 16 bits 1 8 1 16 nop 0001 010x din drdy 0001 011x sdatac
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 rdata ? read data once. the rdata command loads the most recent conversion result into the output register. after issuing this command, the conversion result can be read out by sending 16 sclks, as shown in figure 46 . this command also works in rdatac mode. when performing multiple reads of the conversion result, the rdata command can be sent when the last eight bits of the conversion result are being shifted out during the course of the first read operation by taking advantage of the duplex communication nature of the spi interface, as shown in figure 47 . figure 46. read data once figure 47. using rdata in full-duplex mode copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 47 product folder link(s): ads1146 ads1147 ads1148 sclk din dout drdy msb 0001 001x lsb 1 8 1 16 nop nop rdata sclk dout din drdy nop nop nop rdata nop nop 1 d[15] d[6] d[1] d[1] d[0] d[9] d[8] d[7] d[14] d[15] d[14] 2 1 2 9 10 7 8 15 16 15 16 d[0]
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com user register read and write commands rreg ? read from registers. this command outputs the data from up to 16 registers, starting with the register address specified as part of the instruction. the number of registers read is one plus the second byte. if the count exceeds the remaining registers, the addresses wrap back to the beginning. 1st command byte: 0010 rrrr , where rrrr is the address of the first register to read. 2nd command byte: 0000 nnnn , where nnnn is the number of bytes to read ? 1. it is not possible to use the full-duplex nature of the spi interface when reading out the register data. for example, a sync command cannot be issued when reading out the vbias and mux1 data, as shown in figure 48 . any command sent during the readout of the register data is ignored. thus, it is advisable to send nop through the din when reading out the register data. figure 48. read from register wreg ? write to registers. this command writes to the registers, starting with the register specified as part of the instruction. the number of registers that are written is one plus the value of the second byte. 1st command byte: 0100 rrrr , where rrrr is the address of the first register to be written. 2nd command byte: 0000 nnnn , where nnnn is the number of bytes to be written ? 1. data byte(s): data to be written to the registers. figure 49. write to register 48 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148 din dout vbias 0010 0001 0000 0001 1st command byte 2nd command byte mux1 data byte data byte din 0100 0010 0000 0001 mux2 sys0 1st command 2nd command data byte data byte
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 calibration commands the ads1146/7/8 provide system and offset calibration commands and a system gain calibration command. sysocal ? offset system calibration. this command initiates a system offset calibration. for a system offset calibration, the input should be externally set to zero. the ofc register is updated when this operation completes. sysgcal ? system gain calibration. this command initiates the system gain calibration. for a system gain calibration, the input should be set to full-scale. the fsc register is updated after this operation. selfocal ? self offset calibration. this command initiates a self-calibration for offset. the device internally shorts the inputs and performs the calibration. the ofc register is updated after this operation. figure 50. calibration command copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 49 product folder link(s): ads1146 ads1147 ads1148 sclk din drdy 1 8 t cal calibration command calibration starts calibration complete
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com application information spi communication examples negative terminal of both sensors (that is, channels ain1 and ain3). all these settings can be changed this section contains several examples of spi by performing a block write operation on the first four communication with the ads1146/7/8, including the registers of the device. after the drdy pin goes low, power-up sequence. the conversion result can be immediately retrieved by sending in 16 spi clock pulses because the device channel multiplexing example defaults to rdatac mode. as the conversion result is being retrieved, the active input channels can be this first example applies only to the ads1147 and switched to ain2 and ain3 by writing into the mux0 ads1148. it explains a method to use the device with register in a full-duplex manner, as shown in two sensors connected to two different analog figure 51 . the write operation is completed with an channels. figure 51 shows the sequence of spi additional eight spi clock pulses. the time from the operations performed on the device. after power-up, write operation into the mux0 register to the next 2 16 system clocks are required before communication drdy low transition is shown in figure 51 and is may be started. during the first 2 16 system clock 0.513ms in this case. after drdy goes low, the cycles, the devices are internally held in a reset state. conversion result can be retrieved and the active in this example, one of the sensors is connected to channel can be switched as before. channels ain0 and ain1 and the other sensor is connected to channels ain2 and ain3. the adc is operated at a data rate of 2ksps. the pga gain is set to 32 for both sensors. vbias is connected to the (1) for f osc = 4.096mhz. figure 51. spi communication sequence for channel multiplexing 50 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148 dvdd start reset cs drdy sclk 3 00 00 00 conversion result for channel 1 power-up sequence adc initial setup multiplexer change is channel 2 data retrieval for channel 2 conversion initial setting:ain0 is the positive channel, ain1 is the negative channel, internal reference selected, pga gain = 32, data rate = 2ksps, vbias is connected to the negative pins ain1 and ain3. ain2 is the positive channel,ain3 is the negative channel. conversion result for channel 2 01 02 03 wreg wreg din dout t drdy 0.513ms for mux0 write nop 16ms (1)
ads1146 ads1147 ads1148 www.ti.com sbas453f ? july 2009 ? revised april 2012 sleep mode example be changed by performing a block write operation on the first four registers of the device. after performing this second example deals with performing one the block write operation, the start pin can be conversion after power-up and then entering into the taken low. the device enters the power-saving sleep power-saving sleep mode. in this example, a sensor mode as soon as drdy goes low 0.575ms after is connected to input channels ain0 and ain1. writing into the sys0 register. the conversion result commands to set up the devices must occur at least can be retrieved even after the device enters sleep 2 16 system clock cycles after powering up the mode by sending 16 spi clock pulses. devices. the adc operates at a data rate of 2ksps. the pga gain is set to 32 for both sensors. vbias is connected to the negative terminal of both the sensors (that is, channel ain1). all these settings can (1) for f osc = 4.096mhz. figure 52. spi communication sequence for entering sleep mode after a conversion copyright ? 2009 ? 2012, texas instruments incorporated submit documentation feedback 51 product folder link(s): ads1146 ads1147 ads1148 dvdd start reset cs drdy sclk 00 conversion result for channel 1 power-up sequence adc initial setup adc is put to sleep after a single conversion. data are retrieved when adc is sleeping. initial setting:ain0 is the positive channel, ain1 is the negative channel, internal reference selected, pga gain = 32, data rate = 2ksps, vbias is connected to the negative pins, ain1 and ain3. adc enters power-saving sleep mode 01 02 03 wreg din dout t drdy (0.575ms) nop 16ms (1)
ads1146 ads1147 ads1148 sbas453f ? july 2009 ? revised april 2012 www.ti.com revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision e (april 2012) to revision f page ? added qfn-32 to listed packages available for the ads1148 in description section ......................................................... 1 ? added ads1148, qfn-32 row to package/ordering information table ............................................................................... 2 ? corrected ads1148 pin description table name ............................................................................................................... 11 changes from revision d (october 2011) to revision e page ? added rhb pin configuration ............................................................................................................................................... 6 changes from revision c (april 2001) to revision d page ? added footnote to analog inputs, full-scale input voltage parameter typical specification in electrical characteristics table ...................................................................................................................................................................................... 3 ? deleted analog inputs, mux leakage current parameter from electrical characteristics table ............................................ 3 ? updated figure 1 to show t cspw timing ............................................................................................................................... 12 ? added t cspw to timing characteristics for figure 1 ............................................................................................................ 12 ? changed t dts minimum specification in timing characteristics for figure 2 ...................................................................... 12 ? added figure 7 , figure 8 , figure 9 , and figure 10 ............................................................................................................ 15 ? added figure 11 , figure 14 , figure 15 , and figure 16 ...................................................................................................... 16 ? corrected figure 19 to remove constant short ................................................................................................................... 18 ? added table 3 to analog input impedance section ............................................................................................................ 19 ? corrected figure 26 and figure 27 .................................................................................................................................... 21 ? added details to bias voltage generation section ............................................................................................................. 23 ? added details to calibration section ................................................................................................................................... 25 ? added equation 8 to calibration section ............................................................................................................................ 25 ? added details to calibration commands section ................................................................................................................ 26 ? added channel cycling and overload recovery section ................................................................................................... 28 ? corrected table 12 ............................................................................................................................................................. 29 ? added details to digital interface section ........................................................................................................................... 30 ? added restricted command to table 18 ............................................................................................................................ 44 52 submit documentation feedback copyright ? 2009 ? 2012, texas instruments incorporated product folder link(s): ads1146 ads1147 ads1148
package option addendum www.ti.com 24-jan-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) top-side markings (4) samples ads1146ipw active tssop pw 16 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 105 ads1146 ads1146ipwr active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 105 ads1146 ads1147ipw active tssop pw 20 70 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 105 ads1147 ads1147ipwr active tssop pw 20 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 105 ads1147 ADS1148IPW active tssop pw 28 50 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 105 ads1148 ADS1148IPWr active tssop pw 28 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 105 ads1148 ads1148irhbr active qfn rhb 32 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 105 ads 1148 ads1148irhbt active qfn rhb 32 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 105 ads 1148 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature.
package option addendum www.ti.com 24-jan-2013 addendum-page 2 (4) only one of markings shown within the brackets will appear on the physical device. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ads1146ipwr tssop pw 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 q1 ads1147ipwr tssop pw 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 q1 ads1148irhbr qfn rhb 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 q2 ads1148irhbt qfn rhb 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 q2 package materials information www.ti.com 5-feb-2013 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ads1146ipwr tssop pw 16 2000 367.0 367.0 35.0 ads1147ipwr tssop pw 20 2000 367.0 367.0 38.0 ads1148irhbr qfn rhb 32 3000 367.0 367.0 35.0 ads1148irhbt qfn rhb 32 250 210.0 185.0 35.0 package materials information www.ti.com 5-feb-2013 pack materials-page 2

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